This invention relates to managing access by a plurality of instruction streams to a shared resource.
The shared resource may be, for example, a vector processor. In vector processing, the same operation is performed on each element of a set (vector) of data. In a vector add operation, for example, the elements of a first data vector are added to the respective elements of a second data vector. Vector processing typically requires specialized hardware, such as a floating point processor and vector registers, together known as a "vector unit".
In multiple processor systems, multiple instruction streams on multiple pipelines often require a vector operation at the same time. Some systems have separate vector units dedicated to the respective instruction streams. Others share a single vector unit among the multiple pipelines. The multiple instruction streams run asynchronously with respect to one another on their pipelines and request access to the vector unit whenever they need to perform a vector operation (i.e., on an "as-needed" basis). Thus, when two or more streams simultaneously request access to the vector unit, neither stream obtains access to the vector unit right away; rather, arbitration is performed between them. The arbitration utilizes valuable vector unit operating time and thus limits throughput.